Integrated circuits comprise many transistors and the electrical interconnections between them. Depending upon the interconnection topology, transistors perform Boolean logic functions like AND, OR, NOT, NOR and are referred to as gates. Some fundamental anatomy of an integrated circuit will be helpful for a full understanding of the factors affecting the flexibility and difficulty to design an integrated circuit. An integrated circuit comprises layers of a semiconductor, usually silicon, with specific areas and specific layers having different concentrations of electron and hole carriers and/or insulators. The electrical conductivity of the layers and of the distinct areas within the layers is determined by the concentration of ions referred to as dopants that are implanted into these areas. In turn, these distinct areas interact with one another to form the transistors, diodes, and other electronic devices.
These devices interact with each other by electromagnetic field interactions or by direct electrical interconnections. Openings or windows are created for electrical connections through the layers by an assortment of processing techniques including masking, layering, and etching additional materials on top of the wafers. These electrical interconnections may be within the semiconductor or may lie above the semiconductor areas using a complex mesh of conductive layers, usually of metal such as aluminum, tungsten, or copper fabricated by deposition on the surface and then selectively removed. Any of these semiconductor or connectivity layers may be separated by insulative layers, e.g., silicon dioxide.
Integrated circuits and chips have become increasingly complex with the speed and capacity of chips doubling about every eighteen months because of the continuous advances in design software, fabrication technology, semiconductor materials, and chip design. An increased density of transistors per square centimeter and faster clock speeds, however, make it increasingly difficult to design and manufacture a chip that performs as actually desired. Unanticipated and sometimes subtle interactions between the transistors and other electronic structures may adversely affect the performance of the circuit. These difficulties increase the expense and risk of designing and fabricating chips, especially those that are custom designed for a specific application. The demand for complex custom designed chips has increased along with the demand for applications and products incorporating microprocessors, yet the time and money required to design chips have become a bottleneck to bring these products to market. Without an assured successful outcome within a specified time, the risks have risen with the costs, and the result is that fewer organizations are willing to attempt the design and manufacture of custom chips.
One of the primary areas of interest in the design of integrated electronic systems is the field of cached processors and related memory blocks and components. Examples of cached processors include ARM (Advanced RISC Machines) and MIPS (Microprocessor without Interlocking Pipeline Stages) processors. Such cached processors can be implemented in the context of a core processor configuration. One example of such a core processor configuration is a processor CoreWare™ (CW) hard macro (HM). Note that “CoreWare” is a trademark of LSI Logic Corporation. A hard macro (HM) is a complete physical implementation and addresses all requirements and design rules of the supported technology. Such a methodology has received wide acceptance in the integrated circuit industry, because implementation issues can be solved readily and the core ware (CW) integration at the chip level is predictable and can be executed efficiently. The hard macro implementation does not offer flexibility when it comes to supported cache size or processor specific configuration options. Thus, the often implemented processor hard macro is actually not a very good fit for typical customer requests.
One solution to these problems was the introduction of a flexible design for memory use in integrated circuits, which has been referred to as a “landing zone” technology or concept, and which results in the implementation of a cached processor. An example of this technology is disclosed in U.S. Patent Application Publication No. US 2005/0108495, entitled “Flexible Design for Memory Use in Integrated Circuits,” which published on May 19, 2005 and is assigned to LSI Logic Corporation of Milpitas, Calif., U.S.A. U.S. Patent Application Publication No. US 2005/0108495, which is incorporated herein by reference in its entirety, generally describes a method for designing and using a partially manufactured semiconductor product is disclosed.
As disclosed in U.S. Patent Application Publication No. US 2005/0108495, the partially manufactured semiconductor product, referred to as a slice, which contains a fabric of configurable transistors and one or more areas of embedded memory. The method contemplates that a range of processors, processing elements, processing circuits exists which might be manufactured as a hard macro or configured from the transistor fabric of the slice. The method then evaluates all the memory requirements of all the processors in the range to create a memory superset to be embedded into the slice. The memory superset can then be mapped and routed to a particular memory for one of the processors within the range; ports can be mapped and routed to access the selected portions of the memory superset. If any memory is not used, then it and/or its adjoining transistor fabric can become a “landing zone” for other functions or registers or memories.
Such technology can be thought of as one possible hard macro methodology, with the additional features of the hard macro constructed on the configurable transistor fabric region of an ASIC platform, also known as an r-cell, and the use of diffused memory resources of the slice. The metal hard macro with known timing characteristics that “snap” to a specific location and set of memories in a given slice as, for example, “integrator 1,” have been recognized by the integrated circuit industry as constituting an innovative concept. Thus, the technology disclosed in U.S. Patent Application Publication No. US 2005/0108495 can be utilized to enable a cached processor on an RC slice family “integrator 1” without the burden of developing processor specific slices.
Such “landing zone” technology, however, has several limitations, including reduced flexibility regarding processor type, the number of processors and the supported cache size. The “landing zone” concept supports only one processor hard macro implementation with a fixed cache size, while the demand from users and customers for multiple processor systems has increased, along with an increased demand for combinations of processor types and varying cache configurations.
One other related technology that has become more popular in recent years is the field of semi-programmable ASIC (Application Specific Integrated Circuit) devices. Integrated circuit foundries have begun to develop standard, or base, platforms, known as “slices” containing the base layers of an integrated circuit but without the metal interconnection layers. The base layers are patterned to form gates that can be configured into cells using tools supplied by the foundry. The chip designer designs additional metal layers for the base platform to thereby configure the integrated circuit into a custom ASIC employing a customer's technology.
An example of such a configurable base platform is the RapidChip® platform available from LSI Logic Corporation of Milpitas, Calif. The RapidChip® platform permits the development of complex, high-density ASICs in minimal time with significantly reduced design and manufacturing risks and costs. The design effort for a semi-programmable ASIC encompasses several stages. After the chip size has been selected and the input-output (I/O) cells have been placed in a layout pattern for the base platform, mega cells, including memories and other large hard macros (i.e., “hardmacs”), are placed. Thereafter, standard cells are placed to complete the chip design.
Consider a base platform containing basic sets of memories of a predetermined type, such as RRAMs. RRAMs are sets of memory of the same type that are placed compactly and have built-in testing and self-repairing capabilities. Usually, IC designers prefer not to use all the available memory sets of the RRAM so that unused memory sets are available for self-repairing processes. The base platform might also contain single memories such as single diffused memories. The design created by the IC designer may contain user-defined memories, herein, sometimes called customer memories, which are mapped into one or more of the pre-defined memory locations on the base platform.
Typically, a customer design includes one or more processors that run a sequence of stored instructions to perform tasks defined by a user program. Different instruction sets are used by different types of processors to complete the tasks defined in the program. For example, general purposes instruction sets are typical of microprocessors. Application specific instruction sets are used when it is required to speed up certain computational tasks. For example, a digital signal processor (DSP) embodies instruction sets that enhance computation of certain mathematical algorithms.
Different implementations of the same instruction sets are possible in hardware with different trade-offs of performance and resources. One common implementation in which this difference arises is how much support memory is available and how that memory is organized. For example, a processor might utilize cache memory for enabling a large address space to be mapped onto a smaller one, by re-using addresses. Another processor might utilize a tightly coupled memory (TCM) having a fixed address space, which is sufficient for most critical instructions of the program. During the design process, the support memory needed to support the processor is mapped to available memory locations that are pre-defined on the base platform, and the processor core is placed relative to the memory location.
The “landing zone” concept described above, while offering a number of advantages, is also limited because of its reduced flexibility with respect to processor type, the number of processors and supported cache sizes. The landing zone concept only supports one processor HM implementation, while the demand from users is for multiple processor systems. It is therefore believed that an all-purpose processor implementation is needed, which can support different types of cache memory architectures.